Sampling systems have a wide range of applications in electronics. For example, sampling systems are frequently found in popular consumer electronic devices such as MP3 players, DVD players and cellular telephones. Other popular uses of sampling systems include those related to data acquisition, test and measurement, and control system applications. More specifically, sampling systems and sample-based technology may be found in the electronic components used to construct such devices, which include analog-to-digital converters, switched capacitor networks, signal acquisition circuitry, comparators, and others.
In some applications, sampling systems employ sample and hold circuits that sample a voltage and maintain it in a storage device so that another circuit can measure or otherwise observe the acquired voltage. However, as is known in the art, the mere act of sampling a signal of interest causes a certain amount of distortion to be imparted to the sampled signal.
The signal distortion produced by components in the sampling circuitry tends to limit the useful voltage and frequency range of an input signal. Such distortion may be produced by various factors such as the non-linear resistance characteristics of switches in the sample and hold circuits, effects associated with turnoff thresholds, bulk effect, switch ratio match variations and process variations, etc. Distortion may also be produced by parasitic capacitances of switches in sampling circuits, signal dependent charge injection by switches in the sampling circuits, non-linear load currents flowing through input source resistances, etc.
A typical prior art sample and hold circuit 100 is shown in FIG. 1. Sample and hold circuit 100 generally includes a switch 110, such as a transistor or transmission gate, coupled between an input terminal 115 and a storage device such as sampling capacitor 120. The impedance of switch 110 can be controlled through a switch impedance control terminal 135, which allows switch 110 to function as an “open circuit” (i.e., have a relatively large impedance) when an “OFF” signal is applied to terminal 135, and alternatively, function as a “short circuit” (i.e., have a relatively low impedance) when an “ON” signal is applied to terminal 135.
When switch 110 is, for example, implemented as an N-channel MOS transistor, switch 110 is ON when voltage is applied to its control node, such as a gate, that is above its conductance threshold, and OFF when voltage is applied to its gate that is below its conductance threshold. As is known in the art, the degree to which switch 100 is turned ON or OFF is dependent on the magnitude of the signal applied at its control node. Thus, for example, switch 110 may be turned ON by applying a signal to its control node just above the conductance threshold, but may be turned on harder, improving conductivity characteristics, by applying a greater voltage. Conversely, switch 110 may be turned OFF if the control voltage drops below the conductivity threshold.
In operation, a time varying input signal is applied to input terminal 115. Control circuit 125 is coupled between command terminal 130 and control terminal 135. Control circuit 125 modulates switch impedance between high (OFF) and low (ON) in response to an external hold command signal applied at command node 130.
Sample and hold circuit 100 has two distinct states usually referred to as a sample state and a hold state. In the sample state, switch 110 is ON (i.e., presents a low impedance between input terminal 115 and sampling capacitor 120) thus forcing the signal on the sampling capacitor 120 to follow the input signal. In the hold state, switch 110 is “OFF” (i.e., presents a high impedance between input terminal 115 and sampling capacitor 120), thus the signal on capacitor 120 is maintained at its previous level and is substantially independent of the input signal.
As is known in the art, switch 110 can be implemented using various electronic and electro-mechanical components including, but not limited to, relays, armature switches, and transistors in various forms, including bipolar junction transistors (BJTs), field effect transistors (FETs), etc.
However, known sample and hold circuits, similar to those described above, suffer from various drawbacks and disadvantages. For example, because of certain properties associated with physical component implementations, switch impedance in the sample state is often not low enough for optimal signal transmission or may vary with the magnitude of the input signal. This may occur, at least in part, because the signal applied to the control node of switch 110 does not turn the transistor ON hard enough or its relation with respect to the device conduction threshold varies due to changes in the magnitude of the input signal.
The resulting undesired effect in the sample state is that the voltage signal stored on capacitor 120 will be different from the input signal applied at input terminal 115. Furthermore the difference between the voltage signal stored on capacitor 120 and the input signal may be a function of the instantaneous value of the input signal. Thus, the signal acquired during the hold state will be an imprecise representation of the input signal, and any subsequent signal processing blocks will be affected by these imprecisions. Such signal distortion becomes increasingly significant as the maximum frequency of the input signal increases and its magnitude becomes comparable with an available power supply range.
The performance of high speed sampling data systems such as analog-to-digital converters is sensitive to variations in time intervals between successive sample operations. This variation may be referred to as a sampling jitter. A component of the sampling jitter is the variation in the time delay from the moment the external hold command is asserted at command terminal 130 to the moment switch 110 enters its hold state (i.e., is OFF). Control circuit 125 typically requires a finite time interval to produce the control signal which will modulate the switch impedance from its sample value to its hold value. If the threshold at which this transition occurs is dependent upon the input signal, the result is sampling jitter. Accordingly, it is generally desirable to minimize the effect of the input signal upon the switch control signal transition threshold.
In an effort to overcome the drawback of sampling jitter, sampling switches are constructed using CMOS transmission gates. Using this implementation, however, with an input signal range comparable to the available power supply, the equivalent switch impedance variation during the sample state becomes significant and introduces increasing amount of distortion as the input signal frequency increases.
An early attempt to solve this problem is described in U.S. Pat. No. 5,170,075 to de Wit. As shown in FIG. 2, which is a general representation of the circuit proposed by de Wit, an input signal 215 is connected directly to a control circuit 225, and coupled to a sampling capacitor 220 through a switch 210. Said switch 210 is constructed using a MOSFET device. Control circuit 225 controls switch impedance via control terminal 235 in response to an external HOLD signal 230 and uses a set of boost capacitors (not shown) coupled to develop a pre-selected voltage, VP, which in the sample state, is superimposed upon the input voltage. The resulting compound voltage is used to control the switch impedance during the sample state. As a result, in the sample state, switch 210 is controlled using a fixed gate-to-channel voltage, which reduces the switch impedance variation with input signal. In addition, the transition threshold between the sample and hold states is determined by the magnitude of VP and is substantially independent from the input voltage.
Other attempts to overcome the disadvantages associated with known sampling circuits are presented in U.S. Pat. Nos. 5,500,612 and 6,118,326. The circuits described therein include significant circuitry coupled through additional switches to a sensitive input terminal. One undesirable consequence of these proposed configurations is an increase in signal dependent loading at the input as well as undesirable kick-back signals during the transition between the sample and the hold states. The additional signal dependent loading may translate into increased signal distortions due to the finite impedance of the external input signal driver.
Moreover, kick-back signals appear (due in part to various impedances present in real implementation) when the pre-selected VP voltage is superimposed upon the input signal. These signals present more difficult settling requirements for the external input signal driver thus increasing power consumption and cost. In addition, while the gate-to-channel voltage characteristics are somewhat improved, the channel-to-body potential still changes with the varying input signal. Consequently, the switch impedance during the sample state continues to vary due to the switch device body effect. Similarly, the transition threshold is also dependent upon the switch device body effect.
Another attempt to overcome the disadvantages associated with known sampling circuits is presented in U.S. Pat. No. 6,329,848 to Maes et al., which employs certain known isolation techniques to reduced loading at the input. More specifically, as shown in FIG. 3, which is a general representation of the circuit proposed by Maes et al., a dedicated buffer amplifier 345 is used to isolate a control circuit 325 from an input terminal 315. A switch 310 is implemented using a MOSFET device with its source and drain terminals coupled to the input terminal 315 and a sampling capacitor 320. A gate terminal 335 and a body terminal 340 are both driven by the control circuit 325.
The circuit of FIG. 3 separately controls gate-to-channel and channel-to-body voltages as a function of the input signal as reproduced by buffer 345 to reduce switch impedance variations during the sample state. In addition, the buffer amplifier 345 tends to reduce the undesirable loading of the input terminal. This approach, however, continues to suffer from various drawbacks. For example, despite some reduction in loading compared with other implementations, this implementation still adds some loading at the input terminal, imparting a certain amount of distortion on the input signal. Moreover, it requires the use of a dedicated buffer amplifier with good settling characteristics and negligible group delay, which is relatively expensive to produce.
Thus, in view of the foregoing, it would be desirable to provide circuitry and methods that improve the performance of electronic sampling systems by reducing signal distortions commonly associated with the physical implementations of such circuits.